A semiconductor circuit has a large number of components such as transistors, logic gates, and diodes that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. To fabricate either a printed circuit board or an integrated circuit, the semiconductor designer can use an Electronic Design Automation (EDA) tool to create a schematic design, such as a schematic semiconductor circuit layout. One advantage to an EDA tool is that it allows the designer to position and connect various shapes representing transistors or semiconductors on a circuit, even when there is a large number of components in the circuit. The semiconductor circuit layout typically contains data layers that correspond to the actual layers to be fabricated in the printed circuit board or the integrated circuit. Such semiconductor circuit layout designs usually have to adhere to a set of predefined criteria referred to as design rules which are unique to the product, product type, or manufacturing process. The design rule verification ensures that the semiconductor circuit layout has been properly executed and that the final semiconductor circuit layout created adheres to certain geometric design rules. Various techniques have been developed to ensure conformance to the semiconductor circuit layout design rules. The semiconductor circuit layout can also be created and edited manually by the semiconductor designer. The semiconductor circuit designer can create and edit the semiconductor circuit layout by means of a semiconductor circuit layout editor.
The semiconductor circuit layout created results in the representation of the semiconductor circuit in various semiconductor circuit layout data formats. These semiconductor circuit layout data formats involve a binary format for the representation of planar geometric shapes and text labels. Further, the semiconductor circuit layout editor involves final physical implementation of a semiconductor circuit design that is controlled through the semiconductor circuit designer modification.
A semiconductor circuit layout database forms a baseline of the semiconductor circuit design and stores semiconductor circuit layouts. When the semiconductor circuit designer wants to edit the semiconductor circuit layout by means of the semiconductor circuit layout editor, the semiconductor circuit designer first opens the semiconductor circuit layout database because the desired semiconductor circuit layout that has to be edited has been created earlier and saved into the semiconductor circuit layout database. The semiconductor designer will typically use a suitable software application that will enable the semiconductor circuit designer to open the desired semiconductor circuit layout, and once opened, the semiconductor circuit designer will be able to view a full layout of the selected semiconductor circuit layout. The semiconductor circuit designer then makes the edits using the semiconductor circuit layout editor, for example, add two more shapes or maybe deleting one or more shapes. After making the edits, the user then saves the edited semiconductor circuit layout back in the semiconductor circuit layout database.
The conventional semiconductor circuit layout database has a specification that does not allow several semiconductor circuit designers to update the semiconductor circuit layout at the same time. In order to control the stopping of multiple semiconductor circuit designers working on the same semiconductor circuit layout at the same time, the semiconductor circuit layout database is usually controlled by a suitable database management system. The database management system is basically a piece of software that does not allow the semiconductor circuit designers to edit the semiconductor circuit layout on the semiconductor circuit layout database unless the semiconductor circuit designer have the right to do it, and to get the right to edit it, the semiconductor circuit designer will first have to check out from the semiconductor circuit layout database. As soon as the semiconductor circuit designer check out the semiconductor circuit layout database, nobody else can check out the semiconductor circuit layout database at the same time. Other semiconductor circuit designers are able to view it, but nobody else can check it out at the same time. Thus, during the check out mode, only the allowed semiconductor circuit designer is able to update the semiconductor circuit layout, and once the semiconductor circuit designer is finished with the editing, the allowed semiconductor circuit designer check in and stores the modifications back in the semiconductor circuit layout database. At this point, other semiconductor circuit designers will be able to access and view the updated semiconductor circuit layout.
The conventional method of editing is not efficient in today's advanced node processes where there is a huge database of semiconductor circuit layouts, and it is desired that various semiconductor circuit designers work together on the this huge database having a collection of semiconductor circuit layouts. With the currently available system, each semiconductor circuit designer has to work one after the other, and there is no present capability to parallelize the tasks. This leads to wastage of both the resources and time. Therefore, there is a need in the art for methods and systems that addresses the above mentioned drawbacks of the conventional editing system employed for the semiconductor circuit layout designs.